Huawei's Kirin 9050 Pro uses two stacked dies for smaller chip

Huawei’s new Kirin 9050 Pro processor combines two dies—a compute die and a memory die—using a stacking method called LogicFolding. Both dies are about 121mm² each, bound with advanced vertical connections, resulting in a smaller footprint than the previous Kirin 9030. Built on SMIC’s N+3 and N+2 processes for compute and memory, it nearly doubles the transistor density of its predecessor and outperforms Google’s latest chip on efficiency.

• Two dies stacked: compute and memory
• Uses SMIC's N+3 and N+2 process nodes
• Footprint smaller than previous Kirin 9030
• About 2x the transistor density
• Reported to outpace Google's Tensor G6 on efficiency