Researchers detail copper stress in silicon vias

A joint team from Purdue and UCLA has shown how the microscopic structure of copper affects the stress left behind in silicon chips when building through-silicon vias (TSVs) — vertical connections between chip layers. They used a 3-micron diameter TSV, heated it to 400°C, then measured leftover stress in the silicon. Raman spectroscopy and electron diffraction let them link copper's internal structure to these stress patterns.

• Studied TSVs with 3-micron diameter copper fills
• Annealed samples at 400°C for one hour
• Measured silicon stress using Raman spectroscopy
• Mapped copper grain structure with electron diffraction