Researchers propose row-parallel computing inside DRAM

A joint academic team from Syracuse University, FAU, and TU Dresden has introduced a DRAM design called RAPID that performs arithmetic operations directly within memory rows. Unlike existing methods requiring costly data rearrangement for compatibility with processors, RAPID enables computations in the same row-parallel format used by CPUs. It does this by adding migration and inversion cells to DRAM subarrays, reducing data reorganization overhead.

• RAPID architecture processes data row-parallel inside DRAM
• Requires small DRAM hardware changes: migration and inversion cells
• Reduces need for costly data layout changes
• Compatible with standard processor data formats