Researchers test backside clock meshes for 2nm chips

A team at UC Santa Cruz has built and analyzed clock distribution networks placed on the back of a 2-nanometer chip wafer. These "backside clock meshes" aim to reduce timing errors and power use in advanced processors, using wiring on the chip's reverse side. The study explored how these networks perform compared to traditional designs, especially with today's extremely small transistors.

• UC Santa Cruz studied clock meshes on the chip's backside
• Tested designs used 2nm nanosheet transistor technology
• Backside power delivery leaves extra metal layers for clocks
• Backside meshes connect through silicon vias, not directly
• Study modeled tradeoffs in performance and wiring use