CFET transistor progress could enable 3T standard cells

Researchers at imec have made strides in CFET—complementary FET—transistor technology that could push logic chip designs to 3-track standard cells, further shrinking chip features beyond current nanosheet approaches. They’ve demonstrated new process modules, including backside contacts and multi-threshold voltage gate stacks, and explored ways to optimize design and manufacturing together. This move to vertically stacked p- and n-type transistors aims to keep Moore’s Law scaling alive well past today’s cutting-edge chips.

• CFET stacks p- and n-type transistors vertically
• New modules improve contacts and voltage control
• Aims to enable 3-track standard cells for higher density
• Supports both monolithic and sequential manufacturing paths