New chip technical papers cover WSe₂ transistors, DRAM and more

Researchers have published new technical papers covering a range of chip innovations, including low-contact-resistance tungsten diselenide (WSe₂) transistors, a new backside clock mesh approach for 2nm gate-all-around field-effect transistors, parallel DRAM row processing, advanced techniques for running large AI models, and a formal security analysis of automotive CAN XL. Also included: new methods for hardware validation. No industry adoption yet.

• WSe₂ transistors lower contact resistance in chips
• New mesh backs up clock signals for 2nm GAAFETs
• DRAM method enables parallel row processing
• AI workloads boosted by improved hardware techniques
• Automotive CAN XL security formally analyzed